//----------------------------------------------------------------------------------------------------
// ID Code      : Panel.h No.0000
// Update Note  :
//
//----------------------------------------------------------------------------------------------------

//#ifdef __MAIN__


#if _PANEL_TYPE == _CMO_LVDS_17
#define _PANEL_DISPLAY_RATIO		_PANEL_4_3

#define _DISP_WID					1280
#define _DISP_LEN					1024

#define LVDS_MAP					LVDS_MAP1

//osd position, according to panel
#define _OSD_HPOSITION_OFFSET           				8
#define _OSD_VPOSITION_OFFSET           				2

//color temp range is _COLORTEMP_MIN ~ _COLORTEMP_MIN+100
#define _CT9300_RED_VGA		44	//9300
#define _CT9300_GREEN_VGA		65
#define _CT9300_BLUE_VGA		50
#define _CT7500_RED_VGA		46	//7500
#define _CT7500_GREEN_VGA		65
#define _CT7500_BLUE_VGA		39
#define _CT6500_RED_VGA		50	//6500
#define _CT6500_GREEN_VGA		65
#define _CT6500_BLUE_VGA		30
#define _CTUSER_RED_VGA		50
#define _CTUSER_GREEN_VGA		50
#define _CTUSER_BLUE_VGA		50

#define _CT9300_RED_HDMI		44	//9300
#define _CT9300_GREEN_HDMI	50
#define _CT9300_BLUE_HDMI		51
#define _CT7500_RED_HDMI		46	//7500
#define _CT7500_GREEN_HDMI       51
#define _CT7500_BLUE_HDMI		38
#define _CT6500_RED_HDMI		49	//6500
#define _CT6500_GREEN_HDMI	50
#define _CT6500_BLUE_HDMI		28
#define _CTUSER_RED_HDMI		50
#define _CTUSER_GREEN_HDMI	50
#define _CTUSER_BLUE_HDMI		50


#define _CT9300_RED_VIDEO		43	//9300
#define _CT9300_GREEN_VIDEO	49
#define _CT9300_BLUE_VIDEO		51
#define _CT7500_RED_VIDEO		44	//7500
#define _CT7500_GREEN_VIDEO	50
#define _CT7500_BLUE_VIDEO		37
#define _CT6500_RED_VIDEO		49	//6500
#define _CT6500_GREEN_VIDEO	50
#define _CT6500_BLUE_VIDEO		28
#define _CTUSER_RED_VIDEO		50
#define _CTUSER_GREEN_VIDEO	50
#define _CTUSER_BLUE_VIDEO		50


#define _CT9300_RED_YPBPR		43	//9300
#define _CT9300_GREEN_YPBPR	49
#define _CT9300_BLUE_YPBPR		51
#define _CT7500_RED_YPBPR		44	//7500
#define _CT7500_GREEN_YPBPR	50
#define _CT7500_BLUE_YPBPR		37
#define _CT6500_RED_YPBPR		49	//6500
#define _CT6500_GREEN_YPBPR	50
#define _CT6500_BLUE_YPBPR		28
#define _CTUSER_RED_YPBPR		50
#define _CTUSER_GREEN_YPBPR	50
#define _CTUSER_BLUE_YPBPR		50

#ifdef __SCALER__

//--------------------------------------------------
// Panel Configuration :
// _DISP_DOUBLE_PORT | _DISP_EO_SWAP | _DISP_RB_SWAP | _DISP_ML_SWAP |
// _DISP_18_BIT | _RSDS_GC_SWAP | _RSDS_HL_SWAP | _RSDS_PN_SWAP,
//--------------------------------------------------
code PanelType Panel[] =
{
    /*{   // CMO LVDS 17
        _PANEL_LVDS,                                        // Panel Style
        _DISP_DOUBLE_PORT | _DISP_24_BIT,                  // Panel Configuration
       

        32,                                                 // Display Horizontal Start Position
        1280,                                               // Display Horizontal Width
        1312,                                               // Display Horizontal End Position

        1408,                                               // Display Horizontal Total Clock Number in One Display Line
        2044,                                               // Maxinum Display Horizontal Total Clock Number in One Display Line
        1380,                                               // Mininum Display Horizontal Total Clock Number in One Display Line

        12,                                                 // Display Vertical Start Position
        1024,                                               // Display Vertical Height
        1036,                                               // Display Vertical End Position

        1072,                                               // Display Vertical Total Line Number in One Frame
        1272,                                               // Maxinum Display Vertical Total Line Number in One Frame
        1034,                                               // Mininum Display Vertical Total Line Number in One Frame

        16,                                                 // Display H Sync Width
        3,                                                  // Display V Sync Height

        135,                                                // Typical Pixel Clock in MHz
        140,                                                // Maxinum Pixel Clock in MHz
        100,                                                // Mininum Pixel Clock in MHz
    },*/
	{   // CMO LVDS 17
        _PANEL_LVDS,                                        // Panel Style
        _DISP_DOUBLE_PORT | _DISP_24_BIT/* | _DISP_EO_SWAP*/,                  // Panel Configuration
       

        32,                                                 // Display Horizontal Start Position
        1280,                                               // Display Horizontal Width
        1312,                                               // Display Horizontal End Position

        1688,                                               // Display Horizontal Total Clock Number in One Display Line
        2060,                                               // Maxinum Display Horizontal Total Clock Number in One Display Line
        1370,                                               // Mininum Display Horizontal Total Clock Number in One Display Line

        16,                                                 // Display Vertical Start Position
        1024,                                               // Display Vertical Height
        1040,                                               // Display Vertical End Position

        1066,                                               // Display Vertical Total Line Number in One Frame
        1400,                                               // Maxinum Display Vertical Total Line Number in One Frame
        1036,                                               // Mininum Display Vertical Total Line Number in One Frame

        16,                                                 // Display H Sync Width
        3,                                                  // Display V Sync Height

        108,                                                // Typical Pixel Clock in MHz
        140,                                                // Maxinum Pixel Clock in MHz
        90,                                                // Mininum Pixel Clock in MHz
    },
};

#else

extern code PanelType Panel[];


#endif

#endif	//#if _PANEL_TYPE == _CMO_LVDS_17