//----------------------------------------------------------------------------------------------------
// ID Code      : Panel.h No.0000
// Update Note  :
//
//----------------------------------------------------------------------------------------------------

//#ifdef __MAIN__


#if _PANEL_TYPE==_AU_LVDS_T315XW01

#define _PANEL_DISPLAY_RATIO		_PANEL_16_9

#define _DISP_WID					1366
#define _DISP_LEN					768

#define LVDS_MAP					LVDS_MAP1

//display ratio mode set
#define _RATIO_16X9					0
#define _RATIO_4X3						1
#define _DISP_RATIO_MIN				_RATIO_16X9
#define _DISP_RATIO_MAX				_RATIO_4X3
#define _DISP_RATIO_MODENUM			(_DISP_RATIO_MAX+1-_DISP_RATIO_MIN)

#define GET_DISP_DHWID_RATIO_16X9	_DISP_WID//((_DISP_LEN/9)*16)
#define GET_DISP_DHSEXT_RATIO_16X9	0//((_DISP_WID-GET_DISP_DHWID_RATIO_16X9)/2)
#define GET_DISP_DHWID_RATIO_4X3		((_DISP_LEN/3)*4)
#define GET_DISP_DHSEXT_RATIO_4X3		((_DISP_WID-GET_DISP_DHWID_RATIO_4X3)/2)

//osd position, according to panel
#define _OSD_HPOSITION_OFFSET           	8
#define _OSD_VPOSITION_OFFSET           	2

#if _PCB_TYPE==_PCB_JPE_28_A00082_0020


//color temp
#define _CT9300_RED_VGA		53	//12000
#define _CT9300_GREEN_VGA		59
#define _CT9300_BLUE_VGA		61
#define _CT7500_RED_VGA		61	//9300
#define _CT7500_GREEN_VGA		65
#define _CT7500_BLUE_VGA		59
#define _CT6500_RED_VGA		62	//6500
#define _CT6500_GREEN_VGA		59
#define _CT6500_BLUE_VGA		40
#define _CTUSER_RED_VGA		50
#define _CTUSER_GREEN_VGA		50
#define _CTUSER_BLUE_VGA		50

//color temp
//#define _CT9300_RED_VGA		48	//9300
//#define _CT9300_GREEN_VGA		59
//#define _CT9300_BLUE_VGA		45
//#define _CT7500_RED_VGA		51	//7500
//#define _CT7500_GREEN_VGA		59
//#define _CT7500_BLUE_VGA		38
//#define _CT6500_RED_VGA		54	//6500
//#define _CT6500_GREEN_VGA		59
//#define _CT6500_BLUE_VGA		33
//#define _CTUSER_RED_VGA		50
//#define _CTUSER_GREEN_VGA		50
//#define _CTUSER_BLUE_VGA		50


#define _CT9300_RED_HDMI		54//49	//1200
#define _CT9300_GREEN_HDMI	    58//58
#define _CT9300_BLUE_HDMI		61//42
#define _CT7500_RED_HDMI		50//54	//9300
#define _CT7500_GREEN_HDMI      54//54
#define _CT7500_BLUE_HDMI		57//50
#define _CT6500_RED_HDMI		68	//6500
#define _CT6500_GREEN_HDMI	60
#define _CT6500_BLUE_HDMI		40
#define _CTUSER_RED_HDMI		50
#define _CTUSER_GREEN_HDMI	50
#define _CTUSER_BLUE_HDMI		50

//normal
#define _CT9300_RED_VIDEO		54//57//57
#define _CT9300_GREEN_VIDEO	    50//50//60
#define _CT9300_BLUE_VIDEO		52//58//52
//warm 49 44 27
#define _CT7500_RED_VIDEO		53	//7500
#define _CT7500_GREEN_VIDEO		59
#define _CT7500_BLUE_VIDEO		36
//cool  47 52 50
#define _CT6500_RED_VIDEO		50//56	//6500
#define _CT6500_GREEN_VIDEO		46//59
#define _CT6500_BLUE_VIDEO		29//31
#define _CTUSER_RED_VIDEO		50
#define _CTUSER_GREEN_VIDEO		50
#define _CTUSER_BLUE_VIDEO		50

#define _CT9300_RED_YPBPR		58//55	//9300
#define _CT9300_GREEN_YPBPR		63//64
#define _CT9300_BLUE_YPBPR		52//45
#define _CT7500_RED_YPBPR		58	//7500
#define _CT7500_GREEN_YPBPR		64
#define _CT7500_BLUE_YPBPR		45
#define _CT6500_RED_YPBPR		61	//6500
#define _CT6500_GREEN_YPBPR		64
#define _CT6500_BLUE_YPBPR		33
#define _CTUSER_RED_YPBPR		50
#define _CTUSER_GREEN_YPBPR		50
#define _CTUSER_BLUE_YPBPR		50

#elif _PCB_TYPE==_PCB_PT2662C1B

//Y=320
#define _CT9300_RED_VGA		48-4	//9300
#define _CT9300_GREEN_VGA		59-4
#define _CT9300_BLUE_VGA		45+5
#define _CT7500_RED_VGA		51-4	//7500
#define _CT7500_GREEN_VGA		59-3
#define _CT7500_BLUE_VGA		38+5
#define _CT6500_RED_VGA		54-3	//6500
#define _CT6500_GREEN_VGA		59-3
#define _CT6500_BLUE_VGA		33+5
#define _CTUSER_RED_VGA		50
#define _CTUSER_GREEN_VGA		50
#define _CTUSER_BLUE_VGA		50

//Y=360
#define _CT9300_RED_HDMI		49-3	//9300
#define _CT9300_GREEN_HDMI	58-3
#define _CT9300_BLUE_HDMI		42+8
#define _CT7500_RED_HDMI		52-3	//7500
#define _CT7500_GREEN_HDMI       58-3
#define _CT7500_BLUE_HDMI		35+8
#define _CT6500_RED_HDMI		55-3	//6500
#define _CT6500_GREEN_HDMI	58-3
#define _CT6500_BLUE_HDMI		30+8
#define _CTUSER_RED_HDMI		50
#define _CTUSER_GREEN_HDMI	50
#define _CTUSER_BLUE_HDMI		50

//Y=360
#define _CT9300_RED_VIDEO		48-3	//9300
#define _CT9300_GREEN_VIDEO	58-3
#define _CT9300_BLUE_VIDEO		42+8
#define _CT7500_RED_VIDEO		53-3	//7500
#define _CT7500_GREEN_VIDEO	59-3
#define _CT7500_BLUE_VIDEO		36+8
#define _CT6500_RED_VIDEO		56-3	//6500
#define _CT6500_GREEN_VIDEO	59-3
#define _CT6500_BLUE_VIDEO		31+8
#define _CTUSER_RED_VIDEO		50
#define _CTUSER_GREEN_VIDEO	50
#define _CTUSER_BLUE_VIDEO		50
//Y=360
#define _CT9300_RED_YPBPR		55-10	//9300
#define _CT9300_GREEN_YPBPR	64-5
#define _CT9300_BLUE_YPBPR		45+5
#define _CT7500_RED_YPBPR		58-10	//7500
#define _CT7500_GREEN_YPBPR	64-5
#define _CT7500_BLUE_YPBPR		45+5
#define _CT6500_RED_YPBPR		61-10	//6500
#define _CT6500_GREEN_YPBPR	64-5
#define _CT6500_BLUE_YPBPR		33+5
#define _CTUSER_RED_YPBPR		50
#define _CTUSER_GREEN_YPBPR	50
#define _CTUSER_BLUE_YPBPR		50

#endif	//#if _PCB_TYPE==_PCB_JPE_28_A00082_0020



#ifdef __SCALER__

#if _DISP_RATIO_M2_SUPPORT
unsigned int code tDispDHWidRatio[_DISP_RATIO_MODENUM]=
{
	GET_DISP_DHWID_RATIO_16X9,
	GET_DISP_DHWID_RATIO_4X3,
};
unsigned int code tDispDHSExtRatio[_DISP_RATIO_MODENUM]=
{
	GET_DISP_DHSEXT_RATIO_16X9,
	GET_DISP_DHSEXT_RATIO_4X3,
};
#endif	//#if _DISP_RATIO_M2_SUPPORT


//--------------------------------------------------
// Panel Configuration :
// _DISP_DOUBLE_PORT | _DISP_EO_SWAP | _DISP_RB_SWAP | _DISP_ML_SWAP |
// _DISP_18_BIT | _RSDS_GC_SWAP | _RSDS_HL_SWAP | _RSDS_PN_SWAP,
//--------------------------------------------------
code PanelType Panel[] =
{
	{   // AU LVDS 26. 1366x768
        _PANEL_LVDS,                                        // Panel Style
        _DISP_SINGLE_PORT | _DISP_24_BIT | _DISP_EO_SWAP,                 // Panel Configuration

        32,                                                 // Display Horizontal Start Position
        1366,                                               // Display Horizontal Width
        1398,                                               // Display Horizontal End Position

        1560,                                               // Display Horizontal Total Clock Number in One Display Line
        1722,                                               // Maxinum Display Horizontal Total Clock Number in One Display Line
        1414,                                               // Mininum Display Horizontal Total Clock Number in One Display Line

        12,                                                 // Display Vertical Start Position
        768,                                               // Display Vertical Height
        780,                                               // Display Vertical End Position

        806,                                               // Display Vertical Total Line Number in One Frame
        822,                                               // Maxinum Display Vertical Total Line Number in One Frame
        789,                                               // Mininum Display Vertical Total Line Number in One Frame

        32,                                                 // Display H Sync Width
        5,                                                  // Display V Sync Height

        76,                                                // Typical Pixel Clock in MHz
        88,                                                // Maxinum Pixel Clock in MHz
        65,                                                // Mininum Pixel Clock in MHz      
		
    },
};

#else

#if _DISP_RATIO_M2_SUPPORT
extern unsigned int code tDispDHWidRatio[_DISP_RATIO_MODENUM];
extern unsigned int code tDispDHSExtRatio[_DISP_RATIO_MODENUM];
#endif	//#if _DISP_RATIO_M2_SUPPORT


extern code PanelType Panel[];


#endif

#endif	//#if _PANEL_TYPE == _AU_LVDS_26