#include "Core\Header\IncludeCD.h" //_VERSION_CODE: 1-9 //_RELEASE_CODE: (1-9)<<4 +(1-9) #define _VERSION_CODE 0x01 //#define _RELEASE_CODE 0x20 // update sva buglist 071016 //#define _RELEASE_CODE 0x21 // update sva buglist 071016 //#define _RELEASE_CODE 0x22 // rebuild map of 24c16, set total channel to 120 //#define _RELEASE_CODE 0x23 // update sleep time countdown hint logic //#define _RELEASE_CODE 0x24 // add ypbpr img osd page //#define _RELEASE_CODE 0x25 // add ypbpr img osd page //#define _RELEASE_CODE 0x26 // video sharpness improve //#define _RELEASE_CODE 0x27 // vga adc pll non lock, disable apll watch dog //#define _RELEASE_CODE 0x28 // video color improve //#define _RELEASE_CODE 0x29 // factory reset update, default VDC bri/con update, colortemp data update //#define _RELEASE_CODE 0x30 // Globalink update pt2660a //#define _RELEASE_CODE 0x31 // Update V scaler down and noise reduction error //#define _RELEASE_CODE 0x32 // color temp data load error, rewrite and correct color temp default data //#define _RELEASE_CODE 0x33 // //#define _RELEASE_CODE 0x34 // Update FW according to RT SVN239 //#define _RELEASE_CODE 0x35 // Update FW RT SVN239: YPBPR 480i error // Update: display ration //#define _RELEASE_CODE 0x40 // //#define _RELEASE_CODE 0x40 // 20071214, update for: code in flash is changed while power up (AC line insert in operation) //#define _RELEASE_CODE 0x41 // 20071228, 480i/576i vertical unstable, reload pict mode data while display for VIDEO/YPBPR mode. //#define _RELEASE_CODE 0x42 // 20080328, update //#define _RELEASE_CODE 0x43 // 20080331, update Sanse //#define _RELEASE_CODE 0x44 // 20080421, update firmware //#define _RELEASE_CODE 0x45 // 20080421, update firmware //#define _RELEASE_CODE 0x46 // 20080509, PT2662F add ycbcr source //#define _RELEASE_CODE 0x50 // 20080512, KTC 57924G 5 key #define _RELEASE_CODE 0x83 // 20080512, new style osd //change 0x53 to 0x54 lbh 09.7.13 //---------------------------------------------------------------------------------------------------- // Basic Settings //---------------------------------------------------------------------------------------------------- // _C_ means customer #define _OVERSCAN_PERCENT_97 _FALSE #define _OVERSCAN_PERCENT_95 _FALSE #define _DEFAULT 0 //xx.xx% #define _OVERSCAN_PERCENT_93_75 1 //93.75% #define _OVERSCAN_PERCENT_95_00 2 //95.00% #define _OVERSCAN_PERCENT_97_00 3 //97.00% #define _OVERSCAN_PANASONIC_SIZE 4 #define _HDMI_OVERSCAN_PERCENT _OVERSCAN_PERCENT_93_75 #define _YPBPR_OVERSCAN_PERCENT _OVERSCAN_PERCENT_93_75 #define _VIDEO8_OVERSCAN_PERCENT _OVERSCAN_PANASONIC_SIZE //#define CONFIG_VBI_SOFT _C_CONFIG_VBI_SOFT // 1 //#undef CONFIG_VBI_ENABLE //_C_CONFIG_VBI_ENABLE// 1 //#undef CONFIG_VBI_VCHIP //_C_CONFIG_VBI_VCHIP // 1 //#define _VBI_ITALIC_ENABLE _C_VBI_ITALIC_ENABLE//_TRUE // _TRUE : Enable Italic Font // _FALSE : Disable Italic Font #define _TRANSPARENT_ENABLE _C_TRANSPARENT_ENABLE #define _TEXTMODE_TIMEOUTE_ENABLE _C_TEXTMODE_TIMEOUTE_ENABLE #define _NEW_DV_CTRL_ENABLE _C_NEW_DV_CTRL_ENABLE /* #ifdef CONFIG_VBI_ENABLE #define _VBI_ENABLE _ENABLE //_C_VBI_ENABLE #define _VBI_INTERRUPT _ENABLE //_C_VBI_INTERRUPT #define _VBI_ITALIC_ENABLE _ENABLE #else #define _VBI_ENABLE _DISABLE //_C_VBI_ENABLE #define _VBI_INTERRUPT _DISABLE //_C_VBI_INTERRUPT #define _VBI_ITALIC_ENABLE _DISABLE #endif */ //#define _VCHIP _C_VCHIP//_ENABLE //#define _VCHIP_TV_RATING _C_VCHIP_TV_RATING//_ENABLE //-------------------------------------------------- // Debug Tool //-------------------------------------------------- #define _NONE 0 #define _KINGMICE 1 #define _ISPACK 2 #define _RS232 3 #define _ISP_FOR_MYSON 4 #define _ISP_FOR_RTD2662_EMCU 5 //Useage: //_RS232: vga ddc function enable by default, // open serial port if press MENU+SRC key while power up //_ISPACK: open parrallel debug port (rtd2120 debug tool 2.0 by evan at 071013) //Other: No defined #define _DEBUG_TOOL _ISPACK//_RS232// //add by czl 070921 #define _HDCP_WR_BY_RS232 _OFF #define _DEBUG_Printf_OUTPUT_CONTROL _OFF//_ON// #define _RS232_TUNER _DISABLE//_ENABLE //Access Philip Tuner(FQ1216/1236) //-------------------------------------------------- // PCB Type //-------------------------------------------------- #define _RTD2553V_VD2612_DTV_IF_PCB 1 // RTD2553V + VD2612 +DTV IF Demo board ver.A #define _RTD2553V_VD2612_DTV_IF_PCB_B 2 #define _RTD2547_VD2613_DTV_IF_A_PCB 3 #define _RTD2533V_VD261X_Eastech2 17 // RTD2533V + VD2612 for Eastec #define _RTD2662_MONITOR_QA_PCB 4 // for 2662 single chip platform #define _RTD2662_LCDTV_DEMO_PCB 5 // for 2662 single chip platform #define _RTD2662_LCDTV_DEMO_PCB2 6 // for 2662 single chip platform #define _PCB_PT2662A 7 // premier 20070800 #define _PCB_PT2660A1A 9 // premier 20070900 //modified by xyw 070927 #define _PCB_PT2662C1B 10 // premier 20070900 //modified by xyw 071128 #define _PCB_JPE_28_A00082_0020 11 // premier 20080324 #define _PCB_PT2662F1A 12 // #define _PCB_PT2662B1C 14 // CGT, 20080421 #define _PCB_PT2660_KTC57924G 15 // KTC, 20080512 #define _PCB_PT2662F1C 16 //SVA dvd //20080818 ccy add #define _PCB_TEST 18 // KTC, 20080512 #define _PCB_TYPE _PCB_TEST//_PCB_PT2662F1A//_PCB_PT2662F1C//_PCB_PT2662C1B//_PCB_PT2662B1C//_PCB_PT2662F1A//_PCB_PT2660_KTC57924G//_PCB_PT2660A1A//_PCB_PT2662C1B//_PCB_PT2662B1C// //------------------------------------------------------- //Key Scan Mode //------------------------------------------------------- #define _GPIO_MODE 0 #define _ADCX_MODE 1 //A-ADC0~4(6 bits) or 8-ADC0~2(10 bits) //------------------------------------------------------- //Ir Handler Mode //------------------------------------------------------- #define _SW_MODE 0 #define _HW_MODE 1 //redefine for each PCB //20080820 ccy modify #if (_PCB_TYPE==_PCB_TEST) #define _VOLUME_PT2314_SUPPORT 0 #define _VOLUME_TDA7496_SUPPORT 1 #define _VOLUME_REVERSE _ON #define _AUDIO_EFFECT_SUPPORT 0 #if defined(DERUN_805_AT080)||defined(HUANA_AT090)||defined(XINHUACE_AT090)||defined(HUARUIAN_1010_N101L6)||defined(HUANA_100IFW1_1081)||defined(KAIERSI_905)||defined(AODELI_968)||defined(KANGMEI_N101L6)||defined( TUOBU_AT090)||defined( ZHONGHENGHUIBO_100IFW1) #define _KEY_SCAN_MODE _GPIO_MODE #elif defined(DERUN_808_HSD100IFW1)||defined(DERUN_1012_CLAA102CN)||defined(XIAOBAWANG_AT090)||defined(HUANA_AT090_768KEY)||defined(HUARUIAN_968A)||defined(DERUN_1012_SHARPLQ104)||defined(SANMU_AT090)||defined(HUARUIAN_968J)||defined(YONGNAN_101PFW2B00)||defined(XIAOBAWANG_BT101W01)||defined(XIAOBAWANG_101PFW2B00) #define _KEY_SCAN_MODE _ADCX_MODE #else #define _KEY_SCAN_MODE _ADCX_MODE #endif #define _IR_HANDLER_MODE _HW_MODE #endif //#elif (_PCB_TYPE==_PCB_PT2662A) //-------------------------------------------------- // Definations of Input Ports //-------------------------------------------------- /*#define _INPUT_PORT_0 0 #define _INPUT_PORT_1 1 #define _INPUT_PORT_2 2 #define _INPUT_PORT_3 3 #define _INPUT_PORT_4 4 #define _INPUT_PORT_5 5 #define _INPUT_PORT_6 6 #define _INPUT_PORT_7 7 #define _INPUT_PORT_8 8 #define _INPUT_PORT_9 9 #define _INPUT_PORT_10 10 #define _INPUTSRC_NUM _C_INPUTSRC_NUM*/ //-------------------------------------------------- // Reset Type //-------------------------------------------------- #define _RESET_IN 0 // MCU reset Scaler #define _RESET_OUT 1 // Scaler reset MCU #define _RESET_TYPE _RESET_OUT //-------------------------------------------------- // Scalar Type //-------------------------------------------------- //Currently _RTD2528R added only //#define _RTD2533B 0 // User File: /User/RTD2533B STD/ ID Code: 0x91 //#define _RTD2023L 1 // User File: /User/RTD2533B STD/ ID Code: 0x11 //#define _RTD2023S 2 // User File: /User/RTD2533B STD/ ID Code: 0x11 //#define _RTD2023L_VB 3 // User File: /User/RTD2533B STD/ ID Code: 0x21 //#define _RTD2023S_VB 4 // User File: /User/RTD2533B STD/ ID Code: 0x21 //#define _RTD2553V 5 // User File: /User/RTD2553V STD/ ID Code: 0xa2 //#define _RTD2525L 6 // User File: /User/RTD2525L STD/ ID Code: 0x31 #define _RTD2528R 7 // User File: /User/RTD2528R STD/ ID Code: 0xC1 #define _RTD2662 8 #define _SCALER_TYPE _RTD2662//_RTD2528R // Golden Debug Mode //-------------------------------------------------- #define _NONE 0 // Disable Golden Mode #define _1024x768_60 1 // 1024 x 768 @ 60Hz #define _1280x1024_60 2 // 1280 x 1024 @ 60Hz #define _GOLDEN_MODE _C_GOLDEN_MODE//_NONE //-------------------------------------------------- // Over Driving Supported //-------------------------------------------------- #define _OD_SUPPORT _OFF //-------------------------------------------------- // HDMI Supported //-------------------------------------------------- #define _HDMI_SUPPORT _ON //-------------------------------------------------- // RTD2528R Set Adjusting ADC offset Method //-------------------------------------------------- #define _ADJUST_BY_FW 0 //Adjust ADC offset by F/W #define _ADJUST_BY_HW_OFF_LINE 1 //Enable Auto Black Level of H/W in Off-line Mode //-------------------------------------------------- // Definitions of MAIN_TYPE //-------------------------------------------------- #define _MAIN_TYPE_DISABLE 0 //000: Disable All Output Pins (PWM, TCON, SDRAM, Display, etc.) #define _MAIN_TYPE_1 1 //001: Configure IC as MCM128 with internal 1Mx16 SDRAM0. #define _MAIN_TYPE_2 2 //010: Configure IC as QFP128. No SDRAM is in use. #define _MAIN_TYPE_3 3 //011: Configure IC as QFP128. Only SDRAM1 (1Mx16) is in use. #define _MAIN_TYPE_4 4 //100: Configure IC as QFP128. Both SDRAM0 and SDRAM1 are in use. #define _MAIN_TYPE_5 5 //101: Reserved. (QFP208 w/o SDRAM) #define _MAIN_TYPE_6 6 //110: Configure IC as QFP208. Only SDRAM1 (1Mx16 or 2Mx32) is in use. #define _MAIN_TYPE_7 7 //111: Configure IC as QFP208. Both SDRAM0 and SDRAM1 are in use. #define _MAIN_TYPE _MAIN_TYPE_1 //-------------------------------------------------- // Video Input Selection //-------------------------------------------------- #define _VIDEO_8_IN 0 #define _VIDEO_16_IN 1 #define _VIDEO_IN _VIDEO_8_IN //------------------------------------------------- #define _OD_COMPRESSION _OFF //-------------------------------------------------- // Definitions of Memory Size //-------------------------------------------------- #define _1M_16BIT_1PCE 16 #define _1M_16BIT_2PCE 32 #define _2M_32BIT_1PCE 32 #define _2M_32BIT_2PCE 64 #define _MEMORY_SIZE _2M_32BIT_2PCE //-------------------------------------------------- // Definitions of Memory Size //-------------------------------------------------- #define _MEMORY_16MB 16 #define _MEMORY_32MB 32 #define _MEMORY_64MB 64 #define _MEMORY_128MB 128 //-------------------------------------------------- // Definitions of Memory Speed //-------------------------------------------------- #define _166MHZ 166 #define _200MHZ 200 #define _MEMORY_SPEED _166MHZ /* MCLK = 100 MHz 120 166 200 M value 1E 25 34 3F N value 02 02 02 02 */ //-------------------------------------------------- // Definitions of MPLL M Code //-------------------------------------------------- #define _MPLL_M_CODE 0x34 //-------------------------------------------------- // Definitions of MPLL N Code //-------------------------------------------------- #define _MPLL_N_CODE 0x02 //-------------------------------------------------- // Definitions of Data Latch Delay //-------------------------------------------------- #define _ROW_WR_DELAY 2 //0~1:Resered, 2~5:2~5 MCLK, 6~7:Resered #define _ROW_RD_DELAY 2 //0~1:Resered, 2~5:2~5 MCLK, 6~7:Resered #define _SDR_ROW_DELAY ((_ROW_WR_DELAY << 3) | (_ROW_RD_DELAY)) #define _SDR_COL_DELAY ((2 << 5) | 0x04) //0~1:Resered, 2~3:2~3 MCLK, 4~7:Resered //-------------------------------------------------- // MCU Type //-------------------------------------------------- #define _WINDBOND_W78E65 0 // If using kingmice, please select this option #define _MYSON_MTV312 1 #define _MYSON_MTV512 2 #define _WELTREND_WT61P4 3 #define _WINDBOND_W79E632 4 #define _REALTEK_RTD2662_EMCU 5 #define _MCU_TYPE _C_MCU_TYPE #define CONFIG_RS232_9600 9600 #define CONFIG_RS232_19200 19200 #define CONFIG_RS232_38400 38400 #define CONFIG_RS232_115200 115200 #define _BaudRate _C_BaudRate //-------------------------------------------------- // Panel Type //-------------------------------------------------- #define _AUO_LVDS_22_WXGA 0 //eric 20070524 AU22 #define _AU_RSDS_17 1 #define _AU_LVDS_15 2 #define _AU_LVDS_20_WSXGA 3 #define _AU_LVDS_20_UXGA 4 #define _CPT_CMO_TTL_20 5 #define _AU_LVDS_26 6 #define _LC171W03 7 #define _CMO_M190A1_19 8 #define _CMO_V270B1_27 9 #define _HANNSTAR_M1905_19 10 #define _AUO_M230UW01_23 11 #define _AU_TTL_20_V4 12 #define _SAMSUNG_LVDS_19_WXGA 13 #define _CMO_LVDS_22_WXGA 14 #define _SUMSANG_LTA320W2_L01 15 #define _CMO_LVDS_19_WIDE 16 #define _CMO_LVDS_17 17 #define _AU_LVDS_24W 18 //1920*1200 #define _HSD_190ME13 19 #define _AU_LVDS_T315XW01 20 #define _SHARP_LVDS_LQ150 21 //hua han demo #define _SAMSUNG_LTM190M2L31 22 #define _LVDS_1280X800 23 #define _AU_M190PW01 24 #define _CMO_M260J1_WUXGA 25 //1920X1200 WUXGA #define _M220Z1_03_WXGA 26 #define _SVA_LVDS_19_WXGA 27 #define _AU_B154EW08 28 //20081008 ccy add #define _MITSUBISHI_LVDS_12 29 #define _LQ121S1LG55 30//800x600 dong add 20091109 #define _LQ110Y3DG01 31//800x480 #define _LQ104V1DG52 32//640x480 dong add 20091214 #define _HSD100IFW1 33 #define _PANEL_TYPE _C_PANEL_TYPE #if defined(DERUN_805_AT080)||defined(INNOLUX_AT090) #define _C_PANEL_TYPE _LQ110Y3DG01 #elif defined(DERUN_1012_SHARPLQ104) #define _C_PANEL_TYPE _LQ104V1DG52 #else #define _C_PANEL_TYPE _HSD100IFW1 #endif #define LVDS_MAP1 0 //LVDS Bit-Mapping Table 1 #define LVDS_MAP2 1 //LVDS Bit-Mapping Table 2 //-------------------------------------------------- // Tuner Type //-------------------------------------------------- #define _PHILIPS_1236 0 #define _PHILIPS_1216 1 #define _XUGUANG 2 #define _SONY_PB466Z 3 #define _XUGUANG_JS6H1 4 #define _XUGUANG_JS6BM131F2 5 #define _THOMSON_8640B 6 #define _LG_H064F 7 #define _XUGUANG_TDQ6PD 8 #define _JS6H1_111 9 #define _GDC8F2E_106L 11 //PAL/NTSC, 38MHz #define _TCL_M27WTS2DI 12 //PAL, adc, 38.9MHz #define _ET5C511_TDA9886ST 14 //JPE using, also apply to XF-6A, JVJ #define _ET6T1E_TDA9886ST 15 //Premier using: GDC ET_6T1E #define _GDC8F1D_QF106L 16 //PAL/SECAM, 38.9 #define _TUNER_NONE 17 // #define _GDC8F2D_106L 18 //PAL/NTSC, 38MHz #define _TUNER_TYPE _C_TUNER_TYPE //-------------------------------------------------- // IF Demo Type //-------------------------------------------------- #define _PHILIPS_TDA9886 0 //-------------------------------------------------- // ColorStandard Type //-------------------------------------------------- /* fjyang20070614 remove #define _NTSC 0 #define _PAL 1 #define _BOTH 2 #define _ColorStandard_TYPE _C_ColorStandard_TYPE */ //-------------------------------------------------- //Nonlinear scale up method //-------------------------------------------------- #define _ROOF 0 #define _BOUL 1 #define _NONLINEAR_SCALEUP_METHOD _C_NONLINEAR_SCALEUP_METHOD //-------------------------------------------------- // Remote Control //-------------------------------------------------- #define _NEC_TYPE 0 #define _PANASONIC_TYPE 1 #define _SONY_TYPE 2 #define _NEC_LIKE_TYPE 3 #define _PHILIPS_RC5_TYPE 4 #define _Eastech_TYPE 5 #define _Sampo_TYPE 6 #define _Triflex_TYPE 7 #define _PERFECT_RC5_TYPE 8 #define _NEC2_TYPE 9 #define _COOLAIR_TYPE 10 #define _Channel_TYPE 11 #define _APEX_TYPE 12 #define _AKAI_NEC_TYPE 13 #define _AKAI_Eastech_TYPE 14 #define _REMOTE_CONTROL _C_REMOTE_CONTROL //-------------------------------------------------- // Color Preference //-------------------------------------------------- #define _REALTEK_STYLE 0 #define _PANASONIC_STYLE 1 #define _COLOR_PREFERENCE _C_COLOR_PREFERENCE //-------------------------------------------------- // VGA/DVI Information(H-Width/V-Height/V-Freq) //-------------------------------------------------- #define _SYNC_TYPE 0 #define _TABLE_TYPE 1 #define _TIMING_INFO_TYPE _C_TIMING_INFO_TYPE //-------------------------------------------------- // VDC Type //-------------------------------------------------- #define _RTD2612 0 #define _RTD2613 1 #define _VDC_TYPE _C_VDC_TYPE //-------------------------------------------------- // Auto Scan Type //-------------------------------------------------- #define _TABLE_WEIGHT_SCAN 0 #define _SEQUENTIAL_SCAN 1 #define _SCAN_TYPE _C_SCAN_TYPE //-------------------------------------------------- // Signal Mode Type //-------------------------------------------------- #define _SIG_MODE_TYPE _C_SIG_MODE_TYPE //-------------------------------------------------- // Definations of Host Interface (Parallel/Serial Port) //-------------------------------------------------- #define _SERIAL_PORT 0 #define _PARALLEL_PORT 1 #define _HOST_INTERFACE _C_HOST_INTERFACE //-------------------------------------------------- // Definations of RTD/MCU Crystal Frequency in KHz //-------------------------------------------------- #define _XTAL12000K 12000 #define _XTAL24576K 24576 // If using kingmice, please select this option #define _XTAL24000K 24000 #define _XTAL40000K 40000 #define _XTAL27000K 27000 #define _XTAL24300K 24300 #define _RTD_XTAL _C_RTD_XTAL #define _MCU_XTAL _C_MCU_XTAL //-------------------------------------------------- // Definitions for First DHS Masking //-------------------------------------------------- #define _DHS_MASK _C_DHS_MASK //-------------------------------------------------- // Definitions for Display Signal //-------------------------------------------------- #define _DVS_INVERT _C_DVS_INVERT #define _DHS_INVERT _C_DHS_INVERT #define _DEN_INVERT _C_DEN_INVERT #define _DISPLAY_INVERT _C_DISPLAY_INVERT //-------------------------------------------------- // Definitions for Display Control //-------------------------------------------------- #define _DISPLAY_CTRL _C_DISPLAY_CTRL //-------------------------------------------------- // TMDS Supported //-------------------------------------------------- #define _TMDS_SUPPORT _C_TMDS_SUPPORT //---------------------------------------------------------------------------------------------------- // Advance Settings //---------------------------------------------------------------------------------------------------- //---------------------------------------------------------------------------------------------------- // GAMMA TYPE Settings //---------------------------------------------------------------------------------------------------- //-------------------------------------------------- // Definitions of Gamma Table Type //-------------------------------------------------- #define _COMPACT_GAMMA_NORMAL_TABLE 0 #define _FULL_GAMMA_NORMAL_TABLE 1 #define _COMPACT_GAMMA_COMPRESS_TABLE 2 #define _FULL_GAMMA_COMPRESS_TABLE 3 #define _FULL_GAMMA_COMPRESS_TABLE2 4 #define _GAMMA_TYPE _C_GAMMA_TYPE //-------------------------------------------------- // Support Timing //-------------------------------------------------- #if _PANEL_TYPE==_CMO_M260J1_WUXGA #define _H_FREQ_MAX 1100 // Unit in 0.1 kHZ #define _H_FREQ_MIN 100 // Unit in 0.1 kHZ #define _V_FREQ_MAX 640 // Unit in 0.1 HZ #define _V_FREQ_MIN 490 // Unit in 0.1 HZ #else #define _H_FREQ_MAX 1100 // Unit in 0.1 kHZ #define _H_FREQ_MIN 100 // Unit in 0.1 kHZ #define _V_FREQ_MAX 780 // Unit in 0.1 HZ #define _V_FREQ_MIN 490 // Unit in 0.1 HZ #endif //-------------------------------------------------- // Support Timing //-------------------------------------------------- /*#define _C_H_FREQ_MAX 1100 // Unit in 0.1 kHZ #define _C_H_FREQ_MIN 100 // Unit in 0.1 kHZ #if _PANEL_TYPE==_CMO_M260J1_WUXGA #define _C_V_FREQ_MAX 650//780 // Unit in 0.1 HZ #else #define _C_V_FREQ_MAX 1300//780 // Unit in 0.1 HZ #endif #define _C_V_FREQ_MIN 20//490 // Unit in 0.1 HZ */ //-------------------------------------------------- // Turn on this function to lock in the +-2MHz range //-------------------------------------------------- #define _AFC_TRACKING _C_AFC_TRACKING //-------------------------------------------------- // Definitions of Nonlinear Scaling //-------------------------------------------------- #define _NONLINEAR_SCALING _C_NONLINEAR_SCALING //-------------------------------------------------- // Definitions of APLL1 M/N Code //-------------------------------------------------- #define _APLL1_M_CODE _C_APLL1_M_CODE #define _APLL1_N_CODE _C_APLL1_N_CODE //-------------------------------------------------- // Definitions of APLL1 M/N Code //-------------------------------------------------- #define _APLL_M_CODE 25 //default = 25 #define _APLL_N_CODE 3 //default = 3 //-------------------------------------------------- // Definitions of DDS P Code //-------------------------------------------------- #define _DDS_P_CODE _C_DDS_P_CODE //-------------------------------------------------- // Definitions of APLL Fast Lock //-------------------------------------------------- #define _APLL_FAST_LOCK _C_APLL_FAST_LOCK //-------------------------------------------------- // Definitions of DPLL N Code //-------------------------------------------------- //20081008 CCY ADD #if (_PANEL_TYPE==_LQ110Y3DG01||_PANEL_TYPE==_LQ121S1LG55||_PANEL_TYPE == _MITSUBISHI_LVDS_12||_PANEL_TYPE==_SHARP_LVDS_LQ150 || _PANEL_TYPE==_SAMSUNG_LTM190M2L31 ||_PANEL_TYPE==_AU_M190PW01||_PANEL_TYPE==_HSD100IFW1) #define _DPLL_N_CODE 16 #else #define _DPLL_N_CODE 8 #endif //-------------------------------------------------- // Definitions of DPLL N Code //-------------------------------------------------- #define _M2PLL_USE _C_M2PLL_USE//_OFF #define _M2PLL_XTAL _C_M2PLL_XTAL #define _RTD_M2PLL_RATIO _C_RTD_M2PLL_RATIO //-------------------------------------------------- // Definitions of ADC Fine Tune Delay (Value == 0 ~ 7) //-------------------------------------------------- #define _ADC_FINE_TUNE_DELAY_RED _C_ADC_FINE_TUNE_DELAY_RED #define _ADC_FINE_TUNE_DELAY_GREEN _C_ADC_FINE_TUNE_DELAY_GREEN #define _ADC_FINE_TUNE_DELAY_BLUE _C_ADC_FINE_TUNE_DELAY_BLUE //-------------------------------------------------- // Definitions of ADC Input Swap Settings (ADC0) //-------------------------------------------------- #define _ADC0_INPUT_SWAP_RG _C_ADC0_INPUT_SWAP_RG #define _ADC0_INPUT_SWAP_RB _C_ADC0_INPUT_SWAP_RB #define _ADC0_INPUT_SWAP_GB _C_ADC0_INPUT_SWAP_GB //-------------------------------------------------- // Definitions of ADC Input Swap Settings (ADC1) //-------------------------------------------------- #define _ADC1_INPUT_SWAP_RG _C_ADC1_INPUT_SWAP_RG #define _ADC1_INPUT_SWAP_RB _C_ADC1_INPUT_SWAP_RB #define _ADC1_INPUT_SWAP_GB _C_ADC1_INPUT_SWAP_GB //-------------------------------------------------- // DVI Long Cable Supported //-------------------------------------------------- #define _DVI_LONG_CABLE_SUPPORT _C_DVI_LONG_CABLE_SUPPORT //-------------------------------------------------- // DVI-I Source Switch (VGA/DVI) Supported //-------------------------------------------------- #define _DVI_I_SOURCE_SWITCH_SUPPORT _C_DVI_I_SOURCE_SWITCH_SUPPORT //-------------------------------------------------- // VGA/DVI Auto Switch (VGA/DVI) Supported //-------------------------------------------------- #define _VGA_DVI_AUTO_SWITCH_SUPPORT _C_VGA_DVI_AUTO_SWITCH_SUPPORT //-------------------------------------------------- // Hsync Type Detection Select of Input VGA Port //-------------------------------------------------- #define _HSYNC_ONLY 0 #define _HSYNC_WITH_SOG 1 #define _HSYNC_WITH_SOG_SOY 2 #define _HSYNC_TYPE_SELECT _HSYNC_WITH_SOG_SOY //The setting only for _A0_VGA_PORT or _A1_VGA_PORT //-------------------------------------------------- // A0 and A1 Hsync Source Swap //-------------------------------------------------- #define _HSYNC_SOURCE_SWAP _OFF //-------------------------------------------------- // HDCP Supported //-------------------------------------------------- #define _HDCP_SUPPORT _C_HDCP_SUPPORT //-------------------------------------------------- //Aspect ratio //-------------------------------------------------- #define _DISPLAY_RATIO_ENABLE _C_DISPLAY_RATIO_ENABLE #define _PANEL_4_3 0 #define _PANEL_16_9 1 //-------------------------------------------------- // Video Supported //-------------------------------------------------- #define _VIDEO_SUPPORT _C_VIDEO_SUPPORT //-------------------------------------------------- // Peaking Filter and Coring Control Supported //-------------------------------------------------- #define _PEAKING_CORING_SUPPORT _C_PEAKING_CORING_SUPPORT //-------------------------------------------------- // YPbPr Supported //-------------------------------------------------- #define _YPBPR_SUPPORT _C_YPBPR_SUPPORT//_ON //-------------------------------------------------- // YPbPr Sync Source //-------------------------------------------------- #define _SOG0 0 #define _SOG1 1 #define _YPBPR_SYNC_SOURCE _C_YPBPR_SYNC_SOURCE //-------------------------------------------------- // YPbPr New Sync Detected //-------------------------------------------------- #define _YPBPR_NEW_SYNC_DETECT _C_YPBPR_NEW_SYNC_DETECT//_ON //-------------------------------------------------- // YPbPr Supported //-------------------------------------------------- #define _DVI_DE_ONLY_SUPPORT _C_DVI_DE_ONLY_SUPPORT //-------------------------------------------------- // Set Different Display Information by Mode //-------------------------------------------------- #define _DISP_INFO_BY_MODE _C_DISP_INFO_BY_MODE//_OFF //-------------------------------------------------- // Set DClk Spread Spectrum Range //-------------------------------------------------- #define _DCLK_SPREAD_RANGE _C_DCLK_SPREAD_RANGE //-------------------------------------------------- // Set Last Line Finetune Method //-------------------------------------------------- #define _LAST_LINE_METHOD_NONE 0 #define _LAST_LINE_METHOD_0 1 // Formula: Tne DEN End to DEN Start Length must be (1280*N) #define _LAST_LINE_METHOD_1 2 // Formula: Tne DEN End to DEN Start Length must be (4096*N + 128) #define _LAST_LINE_METHOD_2 3 // Formula: Last line limit #define _LAST_LINE_FINETUNE _C_LAST_LINE_FINETUNE //-------------------------------------------------- // Hardware Load Font Supported (Only No Swap) //-------------------------------------------------- #define _HARDWARE_LOAD_FONT _ON //-------------------------------------------------- // Audio PLL Lock Mode //-------------------------------------------------- #define _HARDWARE_TRACKING 0 #define _N_CTS 1 #define _AUDIO_LOCK_MODE _N_CTS// _N_CTS //-------------------------------------------------- // Set Adjusting Vertical Position Direction Method //-------------------------------------------------- #define _V_POSITION_METHOD_0 0 #define _V_POSITION_METHOD_1 1 #define _V_POSITION_DIRECTION _C_V_POSITION_DIRECTION //----------------------------------------------------- // Set After Auto Adjusting Horizontal and Vertical Position to 50 //----------------------------------------------------- //efine H_V_POSITION_DEFAULT _C_H_V_POSITION_DEFAULT//_FALSE //-------------------------------------------------- // RTD2553V Set Method of Hsync Type Detection for Analog Input //-------------------------------------------------- #define _NORMAL_RUN 0 #define _AUTO_RUN 1 #define _HSYNC_TYPE_DETECTION _C_HSYNC_TYPE_DETECTION//_AUTO_RUN #define _LD_OPTION _C_LD_OPTION //-------------------------------------------------- // RTD2610 SECAM Color Identify //-------------------------------------------------- #define _SECAM_DETECT _C_SECAM_DETECT //ddc support for digital port 0, port 1 uncomplete #define _HDMI_EDID_RW _OFF//_ON// //-------------------------------------------------- // DAC Chip Supported //-------------------------------------------------- #if(_HDMI_SUPPORT == _ON) #define _DAC_SUPPORT _OFF #if _HDMI_EDID_RW #define _HDMI_EDID _ON //Interior HDMI DDC ON/OFF #else //#if _HDMI_EDID_RW #define _HDMI_EDID _OFF//_ON Interior HDMI DDC ON/OFF #endif //#if _HDMI_EDID_RW #else #define _DAC_SUPPORT _OFF #define _HDMI_EDID _OFF #endif //-------------------------------------------------- // Interior HDMI DDC Channel Select //-------------------------------------------------- //#define _DDC2 0 //#define _DDC3 1 #define _HDMI_DDC_CHANNEL_SELECT _DDC2 //-------------------------------------------------- // Interior VGA EDID //-------------------------------------------------- //20080421, DDC support for VGA. start... #define _VGA_EDID _ON //20080421, DDC support for VGA. end... //-------------------------------------------------- // Set TV Nosignal Background //-------------------------------------------------- #define _BLACK_BACKGROUND 0 #define _BLUE_BACKGROUND 1 #define _SNOW_BACKGROUND 2 #define _TV_NOSIGNAL_BACKGROUND _C_TV_NOSIGNAL_BACKGROUND//_BLUE_BACKGROUND #define _BLACK_LEVEL _C_BLACK_LEVEL //-------------------------------------------------- // Set Customer //-------------------------------------------------- // 060727 add ISP Hot key,Menu Key + Source Key #define ISPHotKey _TRUE //------------------------------------------------------- // Protection TV weak signal enter reset mode. //------------------------------------------------------- #define _TV_Weak_Signal_Protection _DISABLE//_ENABLE //-------------------------------------------------- // DVI Supported //-------------------------------------------------- #define _DVI_SUPPORT _C_DVI_SUPPORT //------------------------------------------------------- // YPBPR Auto SOY function //------------------------------------------------------- #define _YPBPR_AUTO_SOY _DISABLE// //------------------------------------------------------- // YPBPR HW Auto SOY function(HW) **_YPBPR_AUTO_SOY and _YPBPR_HW_AUTO_SOY can't enable at the same time //------------------------------------------------------- #define _YPBPR_HW_AUTO_SOY _ENABLE// //------------------------------------------------------- // De-Interlace Supported //------------------------------------------------------- #define _DE_INTERLACE_SUPPORT _ON //------------------------------------------------------- // //------------------------------------------------------- #define _DCC_FUNC _DISABLE //------------------------------------------------------- // AV Output //------------------------------------------------------- #define _AV_OUT _C_AV_OUT //------------------------------------------------------- // AdjustCustomerColorMode //------------------------------------------------------- #define _AdjustCustomerColorMode _C_AdjustCustomerColorMode //731301*** //-------------------------------------------------- // Audio Output Type of HDMI //-------------------------------------------------- #define _I2S 0 #define _SPDIF 1 #define _HDMI_AUDIO_OUTPUT_TYPE _C_HDMI_AUDIO_OUTPUT_TYPE //731301### //741001*** //-------------------------------------------------- // HDMI HOT PLUG OPTION //-------------------------------------------------- #define _HDMI_HOT_PLUG_OPTION _C_HDMI_HOT_PLUG_OPTION//off //-------------------------------------------------- // YPbPr source non-check APLL unlock for DVD player //-------------------------------------------------- #define _YPBPR_NONE_CHECK_APLL _ENABLE// _DISABLE//eric 20070606 //-------------------------------------------------- // YPBPR AUTO COLOR OPTION //-------------------------------------------------- #define _ORIGINAL_TYPE 0 #define _NEW_TYPE 1 #define _YPBPR_AUTO_TYPE _ORIGINAL_TYPE//_NEW_TYPE// //-------------------------------------------------- // De-Interlace TEST OPTION //-------------------------------------------------- #define _DE_INTERLACE_TEST_OPTION _ENABLE //--------------------------------------------------- //if enable need chage _C_MCU_XTAL //--------------------------------------------------- #define _SPEED_UP_FLASH _DISABLE//_ENABLE// //-------------------------------------------------- // Memory Location at Eeprom or Flash //-------------------------------------------------- #define _EEPROM 0 #define _FLASH 1 #define _MEMORY_LOCATION _EEPROM//_FLASH// #define _EXTERNAL_FLASH_TABLE _OFF #if (_SPEED_UP_FLASH) //-------------------------------------------------- // Definitions of MCU Clock Divider Number //-------------------------------------------------- #define _DIV_1 1 #define _DIV_2 2 #define _DIV_3 3 #define _DIV_4 4 #define _DIV_5 5 #define _DIV_6 6 #define _DIV_7 7 #define _DIV_8 8 #define _DIV_9 9 #define _M2PLL_CLK_MHZ 243 #define _FLASH_CLK_80MHZ (_M2PLL_CLK_MHZ/80) // 3 #define _FLASH_CLK_60MHZ (_M2PLL_CLK_MHZ/60) // 4 #define _FLASH_CLK_48MHZ (_M2PLL_CLK_MHZ/48) // 5 #define _FLASH_CLK_34MHZ (_M2PLL_CLK_MHZ/34) // 6 #define _FLASH_CLK_27MHZ (_M2PLL_CLK_MHZ/27) // 7 #define _FLASH_CLK_DIV _FLASH_CLK_48MHZ #define _TURBO_MODE _OFF #if(_FLASH_CLK_DIV == _FLASH_CLK_27MHZ) #define _FAST_READ _OFF #else #define _FAST_READ _ON #endif #if(_FLASH_CLK_DIV > _FLASH_CLK_48MHZ) #define _MCU_CLK_DIV _DIV_1 #else #define _MCU_CLK_DIV _DIV_2 #endif #else//#if (_SPEED_UP_FLASH) #define _FAST_READ _OFF #endif//#if (_SPEED_UP_FLASH) //20080829 ccy modify #define SKYWORTH_OSD _DISABLE//_ENABLE//_DISABLE//_DISABLE//_ENABLE #define SKYWORTH_DISPLAYPROTECT _ENABLE//_DISABLE//_ENABLE #define NOSIGNAL_AUTOOFF_ENABLE _ENABLE//_DISABLE //--------------------------------------- //2660 DC restore compare level //--------------------------------------- #define _SOY_LEVEL 0x20 //--------------------------------------- //2660 DC restore resister //--------------------------------------- #define _SOY_RESISTER _BIT0 // 0 ~ 3 //-------------------------------------------------------------------- //---------------------------------- //xyw fix Power On error //----------------------------------- #define _FIX_POWER_ON_ERROR 1 #define _FIX_CHANGE_SOURCE_ERROR 1 //#define _FIX_BRIGHTNESS_CAN_NOT_ADJUST 1 // backtrack 070810 review this #define _FIX_HDMI_ERROR 1 //-------------------------------------------------- // OSD Adjustment Range Definitions. //-------------------------------------------------- #define _OSD_HPOSITION_RANGE 100 #define _OSD_VPOSITION_RANGE 100 #define _OSD_HPOSITION_START 0 #define _OSD_VPOSITION_START 0 #if _PANEL_TYPE ==_AUO_LVDS_22_WXGA #define _OSD_UMAIN_DH_END (360-40+8) //User main page #define _OSD_UMAIN_DV_END (320-20) #elif _PANEL_TYPE==_M220Z1_03_WXGA #define _OSD_UMAIN_DH_END (360-40+8) //User main page #define _OSD_UMAIN_DV_END (320-20) #elif _PANEL_TYPE==_SAMSUNG_LTM190M2L31 #define _OSD_UMAIN_DH_END (360-40+8-40) //User main page #define _OSD_UMAIN_DV_END (320-20+8) #elif _PANEL_TYPE==_SAMSUNG_LVDS_19_WXGA #define _OSD_UMAIN_DH_END (360-40+8-40) //User main page #define _OSD_UMAIN_DV_END (320-20+8) #elif _PANEL_TYPE==_SVA_LVDS_19_WXGA #define _OSD_UMAIN_DH_END (360-40+8-40) //User main page #define _OSD_UMAIN_DV_END (320-20+8) #elif 1//_PANEL_TYPE==_CMO_LVDS_17 #define _OSD_UMAIN_DH_END (360) //User main page//20080901 #define _OSD_UMAIN_DV_END (340) //20080919 ccy modify #endif //#if _CUSTOMER_CGT //-------------------------------------------------------------------- #define _HPC_OTHER_IR_FUCTION_ENABLE 1 //---------------------------------------------------------------------- #define _POWER_ON_LOGO_SUPPROT _OFF//_ON// _OFF #define _POWER_ON_LOGO_NONE 0 #define _POWER_ON_LOGO_AIFA 1 #define _POWER_ON_LOGO_JPE 2 //20080826 ccy add #define _POWER_ON_LOGO_OSTAR 3 #define _POWER_ON_LOGO_TYPE _C_POWER_ON_LOGO_TYPE //-------------------------------------------------- // Chinese Font Type dong add 20080731 //-------------------------------------------------- #define _CH_FONT_2X1 0 #define _CH_FONT_1X1 1 #define _CHINESE_FONT_TYPE _C_CHINESE_FONT_TYPE //-------------------------------------------- //add by xyw for jpe #define _PICTURE_MODE_ONLY_USE_4_ 1 #define _OSD_ADD_SLEEP_FUNCTION 1 #define _ALL_SOURCE_USE_BLUE_BACKGROUND 1 //add by xyw 080220 #define _USE_DISPLAY_FUNCTION 1 //add by xyw 080222 #define _USE_SYSTEM_KEY_FUNCTION 1 //add by xyw 080222 #define _USE_MISC_KEY_STATE 1 //add by xyw 080313 #define _TV_WEAKE_SIGNAL_ 0 // color burst unclocked by CZL 080313 #define _COLOR_BURST_UNLOCK 0 // color burst unclocked by xyw 080314 #define _BURNIN_MODE_FOR_JPE 1 // disable ICM 080317 #define _DISABLE_ICM 1 // ADD 080319 #define _USE_POWER_SAVING_FOR_JPE 1 // ADD 080319 #define _TV_USE_TAKEOVER 1 //20080331, short menu #define _SHORTMENU_BRI 1 #define _SHORTMENU_CONTRAST 1 #define _SHORTMENU_COLOR 1 //---------------------------------------------------------------------- #define _TYPEOF_OSD_KONSTA 1 #define _MAX_EVENT_AMOUNT 7 //dong add 20080813 #define _AUTO_SCAN_EXIT_TYPE1_ 0 #define _AUTO_SCAN_EXIT_TYPE2_ 1 #define _AUTO_SCAN_EXIT_TYPE _C_AUTO_SCAN_EXIT_TYPE //dong add new type of load euro language 20080815 #define _LOAD_EURO_LANGUAGE_TYPE1_ 0 #define _LOAD_EURO_LANGUAGE_TYPE2_ 1 #define _LOAD_EURO_LANGUAGE_TYPE _C_LOAD_EURO_LANGUAGE_TYPE //20081126, PQ finetune //todo: GAMMA/COLOR TEMP/CONTRAST/BRIGHTNESS #define _PQ_FINETUNE 1 #define _BACKLIGHT_REVERSE 0 //dong add 20091023 #define _TV_WEAK_SIGNAL_THRESHOLD 1//add 20091125 //add by lbh 20100106 #define _NEW_TIME_POWEROFF_TYPE 1 #define _NEW_TIME_POWERON_TYPE 1 #define _FLASH_PROTECT_SUPPORT _ON//_OFF// //090427 #define _SPI_FLASH_EN25F40 _ON//_OFF//